Digital Logic Design & applications
Decimal, Binary, Octal and hexadecimal number system and conversion, Binary weighted codes and inter-conversion, Binary arithmetic including 1's complement and 2's complement, Error detection and correction codes.
Boolean Algebra and Combinational Logic
Boolean algebra theorems, Realization of switching functions using logic gates, Canonical logic forms, Sum of product and product of sums, Karnaugh maps, Simplification of expressions, Variable entered maps, Quine-McCluskey minimization techniques, Mixed logic combinational circuits and multiple output functions.
Analysis and Design of Combinational Logic
Combinational circuit, Decoder, Encoder, Priority encoder, Multiplexers as function generators, Binary adder, Subtractor. BCD adder, Binary comparator, Arithmetic and logic units.
Sequential Logic : Sequential Circuits, Analysis and Design
Triggered flip-flops, Timing specifications, Asynchronous and synchronous counters, Counter design with state equations, Registers, Bidirectional shift registers.
Programmable Logic Devices
PLAs, PALs, CPLD, FPGA Architectures, Finite state machines - Mealy and Moore design, Introduction to VHDL, Implementation of above combinational and sequential circuits using VHDL , Examples of system design applications like Washing machine, Candy vending machine, Traffic lights.
Computer aided synthesis and optimization, Circuit models, Synthesis, Optimization, Computer aided simulation, Verification, Testing and design for testability.
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Review Questions 1
Chapter 1 Number Systems and Codes 11 to 182
Logic Gates j 3J to 356
Solved Examples 344
Review Questions 356
Chapter 10 Sequential Circuit Design with VHDL 101 to 10 70
Chapter 5 Introduction to VHDL 51fo5122
Chapter 11 Programmable Logic Devices 11 1 to 11
Chapter 6 RipFlops 61 to 636
Chapter6 FlipFlops 61 to 636
Solved Examples 633
Chapter7 Registers 71 to 734
Solved Examples 7
Chapter9 Finite State Machines 9 1 to 972
Chapter10 Sequential Circuit Design with VHDL 101 to 1070
Chapter12 CAD Tools
Chapter 2 Boolean Algebra and Theorems 21 to 288
Chapter 3 Logic Gates 31 to 356
Chapter 5 Introduction to VHDL 51 to 5122
Chapter12 CAD Tools 121 to 1210
Solved University Question Papers P1toP62
16-cell map 2-input 2's complement ABCD active low adjacent architecture BC BC binary number Boolean expression Boolean function buffer carry CD CD CD cell clock pulse column Convert counter Cout decimal number decoder downto enable input end component END PROCESS entity Example Excess-3 excitation table full adder full-adder gray code Hamming code hexadecimal HIGH IEEE.std_logic_1164.all implement input variables Inputs Outputs integer inverter JK flip-flop K-map simplification Karnaugh map latch LIBRARY IEEE Logic diagram logic gates logic symbol macrocell maxterms minterms multiplexer NAND gate octal operation parallel parity bit port map prime implicant product terms quad Refer section Reset sequence sequential circuit serial shift register shown in Fig shows signal simplified Solution SOP form STD_LOGIC_VECTOR stdlogic Step subtraction sum of products sum terms synchronous Theorem truth table VHDL code waveforms